>>Hope this makes sense. After doing some reading, I
>>wonder that if L1 and L2 cache is made up of SRAM,
>>which has a response time no faster than about 5
>>nanoseconds, is this a limitation as processor
>>speeds get faster than 200 MHZ? I mean, do the
>>fastest processors have to wait for SRAM cache?


I thought this over(while mowing grass) and think
I understand it better
now. First, I read that the response time of a
chip is the time from
when the chip is signaled until the time that the
required voltages are
available on the chip's pins. Second, a 200MHZ cpu
can "put out" some
kind of signal every 5 nanoseconds. So I was
thinking that if a 200 MHZ
cpu requested data from its cache, that the cache
had 5 nanoseconds to
give the cpu what it wanted so that the CPU could
work with that data.
But with the modern CPUs, that probably wouldn't
matter because they can
do other things; things which have to be done
anyway; so if they don't
get the data from the cache in 5 nanoseconds, it
won't slow down the
system. [I don't know what the fastest response
time of SRAM cache is. I
just guessed 5 nanoseconds.]
So, my conclusion is that SRAM cache can't keep up
with the core processor
clock,[on fast CPUs] but it doesn't mean wait
states have to be added
because the processor should know how many cycles
later it can check its
cache, so it does other things meanwhile.
Someone please correct me if this is wrong.
Thanks
Brad Britton