On 18 Nov 98 at 10:52, Mark Rode wrote:

> I have two FIC PA 2207 Boards....one of them uses a Intel 233MMX processor
> with SDRAM and the other uses a Cyrix 686L 200 processor with EDO. There is
> a Bios setting called CPU Pipeline...the manual describes this as
>
> >CPU Pipeline
> >  When enabled, allows the CPU to execute the pipeline function....
> >  Enabled is Default

  I believe you are describing the FIC PA-2007 board, right?

  There is a long-standing (but not particularly honourable...)
tradition of BIOS options whose descriptions are similarly brief and
unhelpful.  The maker of "TweakBIOS" also sells a BIOS handbook,
about an inch thick, that is often able to clarify such options, but
my copy is at home.

  [See below....]

> another source describes this process as
>
> >pipeline processing
> >       A category of techniques that provide simultaneous, or parallel, processing
> >within the computer  It refers to overlapping operations by moving data or
> >instructions into a conceptual pipe with all stages of the pipe processing
> >simultaneously.  For example, while one instruction is being executed, the
> >computer is decoding the next instruction.  In vector processors, several
> >steps in a floating point operation can be processed simultaneously.

  This is a decent general description of what pipelining is.
Cache operations can be pipelined.  The FPU on current/recent Intel
CPUs is pipelined.
  Much of the speed improvement from the 486 to Pentium at equivalent
clock rates is due to increased use of pipelining in the CPU design.

  Searching Intel's manuals and AMD's book about the K6-2, I find no
reference to a single "CPU pipeline, and no signal to the CPU that is
likely to reflect this setting.
  [Apparently the setting also exists on the FIC VA-503+, which I
have.  I'll check tonight and see how I have it set, and whether
changing it makes a noticeable difference.]

David G

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