On 2 Apr 99, at 10:35, David Nasser wrote:

> Is it in any way reasonable to conceptualize TOE (Time Of Execution)
> for a simple fetch instruction as:
>
>   TOE = Tb + Tma + Tb
>
> where Tb is time required for transfer on the mem. bus and
> Tma is time required for memory access (address resolution, etc) ?
> If this is massively inaccurate, do you have a better model?

  This was basically true until the Compaq 386 came out around 1986-7.
Ever since then, "Tma" has stopped being a constant, so measurements of
Tma (and thus of TOE) have had to embody certain assumptions.

  [I believe most of the variables have to do with how different memory
technologies allow "address resolution, etc" to be handled when adjacent
addresses are accessed.
  Some systems have been able to overlap some work by interleaving banks.
Some support "burst" modes or other ways to reduce Tma and perhaps
eliminate the first Tb.  I'm afraid I'm not up to speed on every
detail.]

  With FPM and earlier technologies, there is no signal when Tma
finishes -- that second Tb is going to start on schedule.  So memory
that uses those technologies *has* to be rated according to the worst
case.  [You may recall an era when system performance was routinely
tweaked by adjusting the number of "wait states" inserted between the
two Tb events....]

> In my insane dream, the Tma for, say, 60 ns EDO, when divided by
> the Tma for 10 ns SDRAM, _approximated_ the ratio of the 2
> ratings (60/10). Crazy, huh?

  My hunch is that we may be seeing a worst-case Tb+Tma+Tb time (FPM
and EDO) compared to a Tma time -- possibly average or best-case -- for
SDRAM.  [I suspect that an accurate model of memory timings is probably
a bit more complicated....]




David G

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