At 08:07 10/31/98 -0500, John Chin wrote:
>Actually, Tag Ram, too, is only part of the equation. The
>chipset will also define the extent of cachable RAM.

But on a Celeron "A" (or on a PII) the L2 is onboard the processor
package and the chipset/motherboard has nothing to do with caching
memory...unless there is L3 cache on the motherboard. I haven't
heard of this happening yet.

Of course, on a socket seven board the chipset ultimately determines
cacheability. (Provided the proper cache is present.)

Regards,
Bill

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