....there is a better definition in your manual then in mine. Yours is also
default off while mine is default on.Maybe the SDRAM is causing  the
problem. If there is no wait state with SDRAM then there wouldn't have any
advanced time to get an a new memory address...........
Mark

>Hi Mark
>
>My manual describes the CPU Pipeline Function thusly:
>"This allows the system controller to signal the CPU for a new memory
>address, even before all data transfers for the current cycle are
>complete, resulting in increased throughput. Enabled means that address
>pipelining is active. The default is disabled."
>
>Okay. You interpret from there.
>
>Bill
>