At 11:41 10/30/98 -0500, John Chin wrote:
>Also, can the Celeron A series with the 128K L2 cache
>cache more than 32MB of RAM?  I recall an old rule
>of thumb that goes: the amount of RAM cachable (in
>Megabytes) is equal to 1/4 the L-2 cache size. Following
>this assertion, the Celeron A could only cache 32MB
>of RAM. True or False?  Facts preferred over opinions
>on this issue, please.

Hi John

This rule of thumb is dangerous. Recall that the Pentium Pro
had 256 KB of L2 cache and this processor could cache the
full 4 GB of physical RAM.

The following (from an old message of mine) might help.

>The amount of addressable memory that can be cached depends
>on the size of the TagRAM, not the total amount of cache memory.
>(L2 is composed of the TagRAM and the burst pipeline synchronous
>static RAM (BSRAM) memories.) The TagRAM holds the memory addresses
>whereas the rest of the L2 memory holds the data that's at those
>addresses. More TagRAM, more addresses to pick from. (Hence more
>"RAM cachable".) Increasing the L2 from 512 KB to 1 MB, say,
>"doubles the depth of the cache lines" but does not change the
>Tag size. It lets you store the data that's at more of the
>addresses at any moment, but does not affect the maximum number
>of addresses that can be chosen from.

Hope this rxplanation helps.

I went to http://developer.intel.com/design/ and downloaded
data sheets and updates for the Celeron 300a (SL2WM, SL32A)
but could not find anything in them concerning the amount of
cacheable RAM.

Regards,
Bill

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