On 2 Feb 99, at 13:53, David Gillett wrote:
> On 1 Feb 99, at 8:13, David Nasser wrote:
>
> > In general, risc processors require _more_ instruction cycles
> > (because the instructions, on average, are more fundamental) to run an
> > application, but execute the individual instructions more quickly. They
> > are sometimes referred to as "load and store" computers because of their
> > instruction's relative (to cisc) simplicity.
>
> On some CISC architectures, there are single complex instructions
> that will change the contents of a specified memory location in
> specified ways. On RISC CPUs, this almost always corresponds to at
> least 3 instructions:
>
> LOAD (mem location -> register)
> <modify value in register>
> STORE (register -> mem location)
>
> A CISC machine often has some kinds of value modification that can be done
> without the separate LOAD and STORE instructions.
> And the use of a register. Because of this consideration, RISC CPUs
> tend to provide many more general-purpose registers than CISC CPUs do.
Actually, the canonical case is "copy a value from location A to
location B". If a machine implements this as a single instruction,
it's almost certainly a CISC architecture. On a RISC machine, this
generally takes the LOAD and STORE instructions as above, and uses a
register.
[This nicely illustrates RISC using smaller, faster, and less-capable
instructions to do the job.]
[In its purest expression, RISC mandates that all instructions be the
same size. Implementing an instruction with room for TWO memory
addresses would mean that the average RISC instruction, already less
powerful than the average CISC instruction, would also be *bigger* than
the average CISC instruction -- CPU speed advantages of RISC would be
more than wiped out by the greater number of larger instructions
bloating the code.]
David G
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