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Tue, 21 Apr 1998 11:03:09 +0000 |
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>
> >>Hope this makes sense. After doing some reading, I
> >>wonder that if L1 and L2 cache is made up of SRAM,
> >>which has a response time no faster than about 5
> >>nanoseconds, is this a limitation as processor
> >>speeds get faster than 200 MHZ? I mean, do the
> >>fastest processors have to wait for SRAM cache?
>
>
>
> I thought this over(while mowing grass) and think
> I understand it better
> now. First, I read that the response time of a
> chip is the time from
> when the chip is signaled until the time that the
> required voltages are
> available on the chip's pins. Second, a 200MHZ cpu
> can "put out" some
> kind of signal every 5 nanoseconds.
No. With a 66 MHz mobo, the clock period is 16 ns; less
with 75, 83, 100 MHz mobos.
Then comes the fact that any cycle requires several periods,
there are wait states, etc.
> Brad Britton
>
************************************
Javier Vizcaino. Ability Electronics. [log in to unmask]
Starting point: (-1)^(-1) = -1
Applying logarithms: (-1)*ln(-1) = ln(-1)
Since ln(-1) <> 0, dividing: -1 = 1 (ln(-1) is complex, but exists)
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