I have two FIC PA 2207 Boards....one of them uses a Intel 233MMX processor
with SDRAM and the other uses a Cyrix 686L 200 processor with EDO. There is
a Bios setting called CPU Pipeline...the manual describes this as

>CPU Pipeline
>When enabled, allows the CPU to execute the pipeline function....Enabled is
>Default

another source describes this process as

>pipeline processing
>       A category of techniques that provide simultaneous, or parallel, processing
>within the computer  It refers to overlapping operations by moving data or
>instructions into a conceptual pipe with all stages of the pipe processing
>simultaneously.  For example, while one instruction is being executed, the
>computer is decoding the next instruction.  In vector processors, several
>steps in a floating point operation can be processed simultaneously.

All of this sounds like a great performance enhancement but I have had very
limited success in getting it to work. If I enable it on the 233MMX it
won't post....it just freezes during the post process. If I enable it on
the Cyrix 686L 200 it works fine BUT if I set the BUS speed down to 66MHz
from 75Hhz it will not post unless I disable CPU Pipeline. I asked Cyrix
about doing this and they said no problem...a 686L 200 will just post and
run as a 686L 166...which is exactly what it posts and runs at as long as
CPU Pipeline is not enabled.

All of this has left me baffled and with the feeling that I am taking a
performance hit on the 233MMX.
Does this have something to do with the SDRAM in the Intel setup ...but why
would CPU Pipeline work with the Cyrix at 75Mhz but not at 66Mhz ? In the
Cyrix case I would be less surprised if it was the reverse.

Perhaps one of our Electrical Engineers could explain this to me so I can
make some sense out of it ?

        thanks
        Mark



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