On 22 Mar 98 at 12:16, Michi Imamura wrote:

> How do the various caches effect the operation in a computer?  For
> example, I know the L2 Cache is essential for boosting the efficiency
> of new systems but how does it work exactly?

  Basically, when an instruction calls for access to memory, several
values get combined to come up with an address.  This goes to the
bus to obtain access to the actual memory location, but it also goes
to the cache controller, where it is split into a high part and a
low part.
  The low part tells which entry in the cache might contain the
sought information.  The entry consists of the data value, and a
"tag" value; the high part of the address is compared to the tag
value to determine if the cached data is really what is wanted.
  [The 64MB caching limit with some chipsets is due to limited
numbers of tag bits to discriminate amongst possible addresses.]

  So either the cache very quickly signals back to the CPU that it
has the data, OR when main RAM, several cycles later, signals back
that it has found the data, it is copied to the cache and then the
cache signals its readiness to the CPU.
  [Recall that FPM and EDO are typically rated to respond in 50-80
ns [and, being DRAM, are subject to refresh which can delay access];
L2 cache SRAM is typically rated at 10-20 ns.]

  How much benefit a piece of code derives from caching depends on
the extent to which it re-uses values still in the cache.
  My rule of thumb has been that L2 cache has better odds of keeping
up with a multiplied CPU (which means 486 DX2, DX4, and all Pentia)
than main RAM does; without L2, there's less point in buying a fast
CPU.

David G