At 01:46 AM 10/31/1998 Bill Cohane wrote:
>
>> . . . . I recall an old rule of thumb that goes:
>>the amount of RAM cachable (in Megabytes)
>>is equal to 1/4 the L-2 cache size.
>
>This rule of thumb is dangerous. . . .
>
>>The amount of addressable memory that can be cached depends
>>on the size of the TagRAM, not the total amount of cache memory.
>>. . . .


Bill:

Sure.  Rules of Thumb are for medieval wife beaters
(couldn't use a branch larger than your thumb) and for
people looking for approximate guidelines for general
circumstances.

I used that old saw to preface the question.  I posed
the question with the awareness that Intel would protect
its P-II product line by crippling the low end. The Celeron
was made to eat into the AMD K-6's market, and I suspect
the Celeron A was made to compete with the AMD K-6/2,
but not fratricidally with its bigger brother.

Actually, Tag Ram, too, is only part of the equation. The
chipset will also define the extent of cachable RAM.

Thanks for your advice, and for looking for the answer.

Regards,

John Chin

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