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Subject:
From:
Brad Britton <[log in to unmask]>
Reply To:
PCBUILD - PC Hardware discussion List <[log in to unmask]>
Date:
Fri, 17 Apr 1998 00:30:52 -0700
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Hope this makes sense. After doing some reading, I
wonder that if L1 and L2 cache is made up of SRAM,
which has a response time no faster than about 5
nanoseconds, is this a limitation as processor
speeds get faster than 200 MHZ? I mean, do the
fastest processors have to wait for SRAM cache?
Probably not, but I am wondering how this
works.THANKS
Brad Britton

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