Hope this makes sense. After doing some reading, I
wonder that if L1 and L2 cache is made up of SRAM,
which has a response time no faster than about 5
nanoseconds, is this a limitation as processor
speeds get faster than 200 MHZ? I mean, do the
fastest processors have to wait for SRAM cache?
Probably not, but I am wondering how this
works.THANKS
Brad Britton